Separation between PMC and PMC-Interconnect to enable multiple PMCs controlled...

Separation between PMC and PMC-Interconnect to enable multiple PMCs controlled by a shared bus interface.

upf.md

@@ -54,6 +54,7 @@ This page describes the changes to the IEEE standard 1801 (UPF 2.1) that were ma
 ### Modeling power management controllers
 
 * configure_time
+* connect_pmc
 * create_pmc
 * schedule_strategy
 * update_device_schedule
@@ -139,56 +140,95 @@ This page describes the changes to the IEEE standard 1801 (UPF 2.1) that were ma
 
 **Example:** *configure_time my_switch -from OFF -to ON -cycles 30*
 
-#### create_pmc
+#### connect_pmc
 
 <table width=100%>
   <tr>
     <th>Purpose</th>
-    <td colspan=2>Create a new power management controller in the current scope that implements the given power state machine.</td>
+    <td colspan=2>Creates a (bus) interface for one or multiple power management controllers so that they can be managed using an on-chip bus interconnect.</td>
   </tr>
   <tr>
     <th>Syntax</th>
-    <td colspan=2><b>create_pmc</b> <i>pmc_name</i>
-<br>[<b>-devices</b> { <i>power_switch | voltage_source</i> }*]
+    <td colspan=2><b>connect_pmc</b> <i>connect_name</i>
+<br><b>-controllers</b> { <i>pmc_ref*</i> }
 <br>[<b>-domain</b> <i>domain_name</i>]
-<br><b>-interface</b> <i>&lt;plain | self | apb3 | axi4lite | avalon | wishbone&gt;</i>
-<br>[<b>-interface_param</b> {<i> name value </i>}]*
-<br>[<b>-extend_interface</b> {<i>target_scope</i>}]
 <br><b>-clock</b> {<i>clock_signal [&lt;posedge|negedge&gt;]</i>}
 <br><b>-reset</b> {<i>reset_signal [&lt;sync|async&gt; &lt;low|high&gt;]</i>}
-<br>[<b>-scheduler</b> <i>&lt;default | custom&gt;]
+<br><b>-bus</b> <i>&lt;apb3 | axi4lite | avalon | wishbone&gt;</i>
+<br>[<b>-bus_param</b> {<i> name value </i>}]*
 </td>
   </tr>
   <tr>
   <th rowspan=10>Arguments</th>
-  <td><i>pmc_name</i></td>
-  <td>The name of the power management controllre to create.</td>
+  <td><i>connect_name</i></td>
+  <td>The name of the power management controller interface to create.</td>
   </tr>
   <tr>
-  <td><b>-devices</b> { <i>power_switch | voltage_source</i> }*</td>
-  <td>Specifies the list of devices that are managed in this power state machine.</td>
+  <td><b>-controllers</b> { <i>pmc_ref</i> *}</td>
+  <td>Specifies the list of power management controllers that are managed by this (bus) interface.</td>
   </tr>
   <tr>
   <td><b>-domain</b> <i>domain_name</i></td>
-  <td>The PMC will be placed in this domain. Make sure, that it is always on or at least always on if any managed power domain shall be on.</td>
+  <td>The interface will be placed in this domain. Make sure, that it is always on or at least always on if any managed power domain shall be on.</td>
+  </tr>
+  <tr>
+  <td><b>-clock</b> {<i>clock_signal [&lt;posedge | negedge&gt;]</i>}</td>
+  <td>Specifies the control signal of the interface and optionally its clock edge (default is posedge).</td>
   </tr>
   <tr>
-  <td><b>-interface</b> <i>&lt;plain | self | apb3 | axi4lite | avalon | wishbone&gt;</i></td>
-  <td>Interface that shall be created to control the PMC by the SoC: Either a plain interface (so timer configuration, mode configuration, status and so on is available as plain inputs and outputs), self-managed interface (uses the conditions specified in describe_state_transition to derive the next power mode) or a variety of bus interfaces (currently: APB3, AXI4-Lite, Avalon-MM, Wishbone) are supported.</td>
+  <td><b>-reset</b> {<i>reset_signal [&lt;sync|async&gt; &lt;low|high&gt;]</i>}</td>
+  <td>Specifies the reset signal and optionally its type (asynchronous/synchronos, active high/low) (default is synchronous active high) for the interface.</td>
+  </tr>
+  <tr>
+  <td><b>-interface</b> <i>&lt;apb3 | axi4lite | avalon | wishbone&gt;</i></td>
+  <td>Interface that shall be created to control the PMC by the SoC. A variety of bus interfaces (currently: APB3, AXI4-Lite, Avalon-MM, Wishbone) are supported.</td>
   </tr>
   <tr>
   <td><b>-interface_param</b> {<i> name value </i>}]*</td>
   <td>Interface parameters, have a look at the documentation.</td>
   </tr>
+</table>
+
+#### create_pmc
+
+<table width=100%>
+  <tr>
+    <th>Purpose</th>
+    <td colspan=2>Create a new power management controller in the current scope that implements the given power state machine.</td>
+  </tr>
+  <tr>
+    <th>Syntax</th>
+    <td colspan=2><b>create_pmc</b> <i>pmc_name</i>
+<br><b>-devices</b> { <i>power_switch | voltage_source | custom_device</i> *}
+<br>[<b>-domain</b> <i>domain_name</i>]
+<br><b>-clock</b> {<i>clock_signal [&lt;posedge|negedge&gt;]</i>}
+<br><b>-reset</b> {<i>reset_signal [&lt;sync|async&gt; &lt;low|high&gt;]</i>}
+<br>[<b>-scheduler</b> <i>&lt;default | custom&gt;]
+<br>[<b>-forward_ports</b> {<i>target_scope</i>}]
+</td>
+  </tr>
+  <tr>
+  <th rowspan=10>Arguments</th>
+  <td><i>pmc_name</i></td>
+  <td>The name of the power management controllre to create.</td>
+  </tr>
   <tr>
-  <td><b>-extend_interface</b> {<i>target_scope</i>}]</td>
-  <td>Extend the interface of the controller to the interface of the given scope (needs to be a parent scope of the power management controller).</td>
+  <td><b>-devices</b> { <i>power_switch | voltage_source</i> *}</td>
+  <td>Specifies the list of devices that are managed in this power state machine.</td>
+  </tr>
+  <tr>
+  <td><b>-domain</b> <i>domain_name</i></td>
+  <td>The PMC will be placed in this domain. Make sure, that it is always on or at least always on if any managed power domain shall be on.</td>
   </tr>
   <tr>
   <td><b>-clock</b> {<i>clock_signal [&lt;posedge | negedge&gt;]</i>}</td>
   <td>Specifies the control signal of the controller and optionally its clock edge (default is posedge).</td>
   </tr>
   <tr>
+  <td>[<b>-forward_ports</b> {<i>target_scope</i>}]</td>
+  <td>Forward the ports of the controller to the interface of the given scope (needs to be a parent scope of the power management controller).</td>
+  </tr>
+  <tr>
   <td><b>-reset</b> {<i>reset_signal [&lt;sync|async&gt; &lt;low|high&gt;]</i>}</td>
   <td>Specifies the reset signal and optionally its type (asynchronous/synchronos, active high/low) (default is synchronous active high) for the controller.</td>
   </tr>
@@ -763,14 +803,14 @@ The following attributes are required for instantiating an APB3 bus interface an
 
 ##### Port List
 
-* i_apb_paddr[addr_width-1:0]: IN
-* i_apb_psel[sel_width-1:0]: IN
-* i_apb_penable: IN
-* o_apb_pready: OUT
-* i_apb_pwrite: IN
-* i_apb_pwdata[data_width-1:0]: IN
-* o_apb_prdata[data_width-1:0]: OUT
-* o_apb_pslverror: OUT (only when use_slave_error is true)
+* apb_paddr_i[addr_width-1:0]: IN
+* apb_psel_i[sel_width-1:0]: IN
+* apb_penable_i: IN
+* apb_pready_o: OUT
+* apb_pwrite_i: IN
+* apb_pwdata_i[data_width-1:0]: IN
+* apb_prdata_o[data_width-1:0]: OUT
+* apb_pslverror_o: OUT (only when use_slave_error is true)
 
 #### AXI4-Lite
 
@@ -790,25 +830,25 @@ The following attributes are required for instantiating an AXI4-Lite bus interfa
 
 ##### Port List
 
-* i_axi_awvalid: IN
-* i_axi_awaddr[addr_width-1:0]: IN
-* i_axi_awprot[2:0]: IN
-* o_axi_awready: OUT
-* i_axi_wavalid: IN
-* i_axi_wdata[data_width-1:0]: IN
-* i_axi_wstrb[data_width/8-1:0]: IN
-* o_axi_wready: OUT
-* i_axi_bready: IN
-* o_axi_bvalid: OUT
-* o_axi_bresp[1:0]: OUT
-* i_axi_arvalid: IN
-* i_axi_araddr[addr_width-1:0]: IN
-* i_axi_arprot[2:0]: IN
-* o_axi_arready: OUT
-* i_axi_rready: IN
-* o_axi_rdata[data_width-1:0]: OUT
-* o_axi_rresp[1:0]: OUT
-* o_axi_rvalid: OUT
+* axi_awvalid_i: IN
+* axi_awaddr_i[addr_width-1:0]: IN
+* axi_awprot_i[2:0]: IN
+* axi_awready_o: OUT
+* axi_wavalid_i: IN
+* axi_wdata_i[data_width-1:0]: IN
+* axi_wstrb_i[data_width/8-1:0]: IN
+* axi_wready_o: OUT
+* axi_bready_i: IN
+* axi_bvalid_o: OUT
+* axi_bresp_o[1:0]: OUT
+* axi_arvalid_i: IN
+* axi_araddr_i[addr_width-1:0]: IN
+* axi_arprot_i[2:0]: IN
+* axi_arready_o: OUT
+* axi_rready_i: IN
+* axi_rdata_o[data_width-1:0]: OUT
+* axi_rresp_o[1:0]: OUT
+* axi_rvalid_o: OUT
 
 #### AvalonMM
 
@@ -828,12 +868,12 @@ The following attributes are required for instantiating a pipelined AvalonMM bus
 
 ##### Port List
 
-* i_avalon_read: IN
-* i_avalon_write: IN
-* i_avalon_address[addr_width-1:0]: IN
-* i_avalon_write_data[data_width-1:0]: IN
-* o_avalon_read_data[data_width-1:0: OUT
-* o_avalon_read_data_valid: OUT
+* avalon_read_i: IN
+* avalon_write_i: IN
+* avalon_address_i[addr_width-1:0]: IN
+* avalon_write_data_i[data_width-1:0]: IN
+* avalon_read_data_o[data_width-1:0: OUT
+* avalon_read_data_valid_o: OUT
 
 
 #### Wishbone
@@ -854,14 +894,14 @@ The following attributes are required for instantiating a simple Wishbone bus in
 
 ##### Port List
 
-* i_wb_cyc: IN
-* o_wb_ack: OUT
-* i_wb_adr[addr_width-1:0]: IN
-* i_wb_dat_m[data_width-1:0]: IN
-* o_wb_dat_s[data_width-1:0]: OUT
-* i_wb_sel[data_width/8-1:0]: IN
-* i_wb_stb: IN
-* i_wb_we: IN
+* wb_cyc_i: IN
+* wb_ack_o: OUT
+* wb_adr_i[addr_width-1:0]: IN
+* wb_dat_m_i[data_width-1:0]: IN
+* wb_dat_s_o[data_width-1:0]: OUT
+* wb_sel_i[data_width/8-1:0]: IN
+* wb_stb_i: IN
+* wb_we_i: IN
 
 ### UPF Interface