Commit fbe42c3d authored by Dustin Peterson's avatar Dustin Peterson

Minor change

parent 4a464144
![commons.eda:extended unified power format](logo.png "commons.eda:extended unified power format")
# Introduction
The classic ASIC design flow supports the specification and implementation of power management mechanisms by means of the Unified Power Format (UPF). A UPF file describes the power design, including power switches, isolation strategies, retention strategies, supply nets, supply ports, power states or even cell mappings. The UPF file references RTL control signals to describe dynamic behavior, for example a designer can specify under which condition a power switch shall toggle or when a component's outputs are isolated. UPF and RTL design can be synthesized by usual RTL synthesis tools such as Synopsys Design Compiler or Cadence Genus.
<img src="classic_flow.png" width="600" />
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