Commit c4f52033 authored by Dustin Peterson's avatar Dustin Peterson

Update bus connect spec.

parent 7a647207
......@@ -151,12 +151,13 @@ This page describes the changes to the IEEE standard 1801 (UPF 2.1) that were ma
<tr>
<th>Syntax</th>
<td colspan=2><b>connect_pmc</b> <i>connect_name</i>
<br><b>-controllers</b> { <i>pmc_ref*</i> }
<br>[<b>-controllers</b> { <i>pmc_ref*</i> }]
<br>[<b>-domain</b> <i>domain_name</i>]
<br><b>-clock</b> {<i>clock_signal [&lt;posedge|negedge&gt;]</i>}
<br><b>-reset</b> {<i>reset_signal [&lt;sync|async&gt; &lt;low|high&gt;]</i>}
<br><b>-bus</b> <i>&lt;apb3 | axi4lite | avalon | wishbone&gt;</i>
<br>[<b>-bus_param</b> {<i> name value </i>}]*
<br>[<b>-custom_register</b> {<i> name default_value </i>}]*
</td>
</tr>
<tr>
......@@ -181,13 +182,17 @@ This page describes the changes to the IEEE standard 1801 (UPF 2.1) that were ma
<td>Specifies the reset signal and optionally its type (asynchronous/synchronos, active high/low) (default is synchronous active high) for the interface.</td>
</tr>
<tr>
<td><b>-interface</b> <i>&lt;apb3 | axi4lite | avalon | wishbone&gt;</i></td>
<td><b>-bus</b> <i>&lt;apb3 | axi4lite | avalon | wishbone&gt;</i></td>
<td>Interface that shall be created to control the PMC by the SoC. A variety of bus interfaces (currently: APB3, AXI4-Lite, Avalon-MM, Wishbone) are supported.</td>
</tr>
<tr>
<td><b>-interface_param</b> {<i> name value </i>}]*</td>
<td><b>-bus_param</b> {<i> name value </i>}]*</td>
<td>Interface parameters, have a look at the documentation.</td>
</tr>
<tr>
<td><b>-custom_register</b> {<i> name default_value </i>}]*</td>
<td>Define additional custom read-write registers, one can use for example to control event-based power mode transitioning.</td>
</tr>
</table>
#### create_pmc
......@@ -241,7 +246,7 @@ This page describes the changes to the IEEE standard 1801 (UPF 2.1) that were ma
</tr>
</table>
**Example:** *create_pmc PMC -domain TOP_PD -devices {my_switch_0 my_voltage_source_x my_custom_device_z} -interface axi4lite -interface_param {addr_width 32} -interface_param {data_width 32} -clock {/i_clk posedge} -reset {/i_rst sync high} -scheduler default*
**Example:** *create_pmc PMC -domain TOP_PD -devices {my_switch_0 my_voltage_source_x my_custom_device_z} -scheduler default*
#### create_voltage_source
......@@ -781,7 +786,53 @@ The library provides a Bus API that is able to automatically generate a bus slav
If you implement all three classes, you need to attach your implementation to the global store by calling *BridgeFactory.add(yourFactory)*.
Three implementations are available currently.
The following implementations are available currently:
#### AHB3-Lite
There is an AHB3-Lite slave interface available, which is implemented by the class *Ahb3LiteBridge* and its related companion object. In order to use it in UPF, use the interface type **ahb3lite**.
##### Required Attributes
The following attributes are required for instantiating a pipelined AHB3-Lite bus interface and shall be specified by adding *-bus_param* to your UPF specification (in *connect_pmc*).
* **addr_width:** Specifies the address width.
* **data_width:** Specifies the data width.
##### Optional Attributes
* **base_address:** Specifies the base address of the bus slave.
* **endianness:** Change bus endianness to either little endian ("little") or big endian ("big"). Defaults to "little".
* **inc_address:** Change increment for register addresses. Defaults to data_width/8.
##### Port List
* ahb_addr_i[addr_width-1:0]: IN
* Address input
* ahb_sel_i: IN
* Selection input
* ahb_ready_i: IN
* Ready input
* ahb_write_i: IN
* Write enable input
* ahb_size_i[2:0]: IN
* Transfer size
* ahb_burst_i[2:0]: IN
* Burst type input
* ahb_prot_i[3:0]: IN
* Slave characteristics of transfer
* ahb_trans_i[1:0]: IN
* Transfer type
* ahb_mastlock_i: IN
* Master lock input
* ahb_wdata_i[data_width-1:0]: IN
* Write data input
* ahb_rdata_o[data_width-1:0]: OUT
* Read data output
* ahb_readyout_o: OUT
* Ready output
* ahb_resp_o: OUT
* Response output
#### APB3
......@@ -789,7 +840,7 @@ There is an AMBA APB3 slave interface available, which is implemented by the cla
##### Required Attributes
The following attributes are required for instantiating an APB3 bus interface and shall be specified by adding *-interface_param* to your UPF specification (in *create_pmc*).
The following attributes are required for instantiating an APB3 bus interface and shall be specified by adding *-bus_param* to your UPF specification (in *connect_pmc*).
* **addr_width:** Specifies the address width.
* **data_width:** Specifies the data width.
......@@ -804,14 +855,22 @@ The following attributes are required for instantiating an APB3 bus interface an
##### Port List
* apb_paddr_i[addr_width-1:0]: IN
* apb_psel_i[sel_width-1:0]: IN
* apb_penable_i: IN
* apb_pready_o: OUT
* apb_pwrite_i: IN
* apb_pwdata_i[data_width-1:0]: IN
* apb_prdata_o[data_width-1:0]: OUT
* apb_pslverror_o: OUT (only when use_slave_error is true)
* apb_addr_i[addr_width-1:0]: IN
* Address input
* apb_sel_i[sel_width-1:0]: IN
* Selection input
* apb_enable_i: IN
* Enable input
* apb_write_i: IN
* Write enable input
* apb_ready_o: OUT
* Ready output
* apb_wdata_i[data_width-1:0]: IN
* Write data input
* apb_rdata_o[data_width-1:0]: OUT
* Read data output
* apb_slverror_o: OUT
* Slave error (only when use_slave_error is true)
#### AXI4-Lite
......@@ -819,7 +878,7 @@ There is an AMBA AXI4-Lite slave interface available, which is implemented by th
##### Required Attributes
The following attributes are required for instantiating an AXI4-Lite bus interface and shall be specified by adding *-interface_param* to your UPF specification (in *create_pmc*).
The following attributes are required for instantiating an AXI4-Lite bus interface and shall be specified by adding *-bus_param* to your UPF specification (in *connect_pmc*).
* **addr_width:** Specifies the address width.
* **data_width:** Specifies the data width.
......@@ -832,24 +891,43 @@ The following attributes are required for instantiating an AXI4-Lite bus interfa
##### Port List
* axi_awvalid_i: IN
* Address Write Channel: Valid input
* axi_awaddr_i[addr_width-1:0]: IN
* Address Write Channel: Address input
* axi_awprot_i[2:0]: IN
* Address Write Channel: Protocol input
* axi_awready_o: OUT
* Address Write Channel: Ready output
* axi_wavalid_i: IN
* Write Data Request Channel: Valid input
* axi_wdata_i[data_width-1:0]: IN
* Write Data Request Channel: Write data input
* axi_wstrb_i[data_width/8-1:0]: IN
* Write Data Request Channel: Strobe input
* axi_wready_o: OUT
* Write Data Request Channel: Ready output
* axi_bready_i: IN
* Write Data Response Channel: Ready input
* axi_bvalid_o: OUT
* Write Data Response Channel: Valid output
* axi_bresp_o[1:0]: OUT
* Write Data Response Channel: Response output
* axi_arvalid_i: IN
* Address Read Channel: Valid input
* axi_araddr_i[addr_width-1:0]: IN
* Address Read Channel: Address input
* axi_arprot_i[2:0]: IN
* Address Read Channel: Protocol input
* axi_arready_o: OUT
* Address Read Channel: Ready output
* axi_rready_i: IN
* Read Data Response Channel: Ready input
* axi_rdata_o[data_width-1:0]: OUT
* Read Data Response Channel: Read data output
* axi_rresp_o[1:0]: OUT
* Read Data Response Channel: Response output
* axi_rvalid_o: OUT
* Read Data Response Channel: Valid output
#### AvalonMM
......@@ -857,7 +935,7 @@ There is an AvalonMM slave interface available, which is implemented by the clas
##### Required Attributes
The following attributes are required for instantiating a pipelined AvalonMM bus interface and shall be specified by adding *-interface_param* to your UPF specification (in *create_pmc*).
The following attributes are required for instantiating a pipelined AvalonMM bus interface and shall be specified by adding *-bus_param* to your UPF specification (in *connect_pmc*).
* **addr_width:** Specifies the address width.
* **data_width:** Specifies the data width.
......@@ -870,12 +948,47 @@ The following attributes are required for instantiating a pipelined AvalonMM bus
##### Port List
* avalon_read_i: IN
* Read select line
* avalon_write_i: IN
* Write select line
* avalon_address_i[addr_width-1:0]: IN
* Address input line
* avalon_write_data_i[data_width-1:0]: IN
* Write data line
* avalon_read_data_o[data_width-1:0: OUT
* Read data line
* avalon_read_data_valid_o: OUT
* Read data line valid flag
#### BRAM
There is a basic ram interface available, which is implemented by the class *BRAMBridge* and its related companion object. In order to use it in UPF, use the interface type **bram**.
##### Required Attributes
The following attributes are required for instantiating a pipelined AvalonMM bus interface and shall be specified by adding *-bus_param* to your UPF specification (in *connect_pmc*).
* **addr_width:** Specifies the address width.
* **data_width:** Specifies the data width.
##### Optional Attributes
* **base_address:** Specifies the base address of the bus slave.
* **endianness:** Change bus endianness to either little endian ("little") or big endian ("big"). Defaults to "little".
* **inc_address:** Change increment for register addresses. Defaults to data_width/8.
##### Port List
* bram_en_i: IN
* Enable line
* bram_we_i: IN
* Write enable line
* bram_addr_i[addr_width-1:0]: IN
* Address input
* bram_wrdata_i[data_width-1:0]: IN
* Write Data input
* bram_rddata_o[data_width-1:0: OUT
* Read data output
#### Wishbone
......@@ -883,7 +996,7 @@ There is a Wishbone slave interface available, which is implemented by the class
##### Required Attributes
The following attributes are required for instantiating a simple Wishbone bus interface and shall be specified by adding *-interface_param* to your UPF specification (in *create_pmc*).
The following attributes are required for instantiating a simple Wishbone bus interface and shall be specified by adding *-bus_param* to your UPF specification (in *connect_pmc*).
* **addr_width:** Specifies the address width.
* **data_width:** Specifies the data width.
......@@ -892,17 +1005,55 @@ The following attributes are required for instantiating a simple Wishbone bus in
* **base_address:** Specifies the base address of the bus slave.
* **endianness:** Change bus endianness to either little endian ("little") or big endian ("big"). Defaults to "little".
* **use_stall:** Activates the stall line. Defaults to false.
* **use_lock:** Activates the lock line. Defaults to false.
* **use_err:** Activates the error line. Defaults to false.
* **use_rty:** Activates the retry line. Defaults to false.
* **use_cti:** Activates the cti line. Defaults to false.
* **use_bte:** Activates the Burst Type Extension. Defaults to false.
* **sel_width:** Size in bits of the selection line. Defaults to 0.
* **tga_width:** Size in bits of the tag address line. Defaults to 0.
* **tgc_width:** Size in bits of the tag cycle line. Defaults to 0.
* **tgd_width:** Size in bits of the tag data line. Defaults to 0.
##### Port List
* wb_cyc_i: IN
* Cycle input
* wb_ack_o: OUT
* Acknowledge output
* wb_adr_i[addr_width-1:0]: IN
* Adress input
* wb_dat_m_i[data_width-1:0]: IN
* Write data input
* wb_dat_s_o[data_width-1:0]: OUT
* wb_sel_i[data_width/8-1:0]: IN
* Read data output
* wb_stb_i: IN
* Strobe input
* wb_we_i: IN
* Write enable input
* wb_sel_i[sel_width-1:0]: IN (only when sel_width > 0)
* Select input array
* wb_stall_o: OUT (only when use_stall is true)
* Stall output
* wb_lock_i: IN (only when use_lock is true)
* Lock input
* wb_err_o: OUT (only when use_err is true)
* Error output
* wb_rty_o: OUT (only when use_rty is true)
* Retry output
* wb_cti_i[2:0]: OUT (only when use_cti is true)
* Cycle type identifier input
* wb_bte_i[1:0]: OUT (only when use_bte is true)
* Burst Type Extension input
* wb_tgd_o[tgd_width-1:0]: OUT (only when tgd_width > 0)
* Data tag type
* wb_tgd_i[tgd_width-1:0]: IN (only when tgd_width > 0)
* Data tag type
* wb_tga_i[tga_width-1:0]: IN (only when tga_width > 0)
* Tag address input
* wb_tgc_i[tgc_width-1:0]: IN (only when tgc_width > 0)
* Tag cycle input
### UPF Interface
......@@ -914,7 +1065,7 @@ The UPF interface highly depends on the power management configuration. Some rul
* For each domain reset strategy an additional control signal, managing the activation and disactivation of the domain reset, will be added. This signal has the right trigger (high/low), depending on the UPF configuration in order to activate/disactive the domain reset at the right time.
* For each power switch and voltage source, the necessary number of control signals (specified with -control_port) will be generated and added to the UPF interface. Each output port matches exactly one control port of a power switch / voltage source and manages these devices so that they switch to the right state at the right time. Furthermore an optional acknowledge input (if an acknowledge port has been specified by -ack_port) will be generated for each voltage source / power switch at the IP's UPF interface, if selected.
Usually the ports will be automatically connected during the UPF translation process &mdash; if you choose not to automatically connect the ports or generate the IP standalone, please have a look at the specific IP documentation.
Usually the ports will be automatically connected during the UPF translation process. If you choose not to automatically connect the ports or generate the IP standalone, please have a look at the specific IP documentation.
### Memory Map
......
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