diff --git a/pages/index.md b/pages/index.md index 5a98d312caafb6be5e70f2b192c52ba84a575167..5154355aca5055bb832fb77273bd33576c161809 100644 --- a/pages/index.md +++ b/pages/index.md @@ -4,6 +4,8 @@ title: Start # Übungen: Parallele Rechnerarchitekturen Sommersemester 2016 +The EInführungsfolien zum simulator finden Sie [hier](static/An_introduction_to_gem5.slides.html) + ## Abgabe ## Übersicht diff --git a/pelicanconf.py b/pelicanconf.py index db03e8cbfd33ada04f9dc7eddc221a5a0ad0228c..c36c12f5587a5b85451fe6f40d8470dcefb9c086 100644 --- a/pelicanconf.py +++ b/pelicanconf.py @@ -8,7 +8,7 @@ SITEURL = 'https://atreus.informatik.uni-tuebingen.de/~gerum/ra/pra/ss16/' PAGE_PATHS=['aufgaben', 'pages'] ARTICLE_PATHS=['news'] -STATIC_PATHS=['aufgaben'] +STATIC_PATHS=['static', 'aufgaben', 'pages'] TIMEZONE = 'Europe/Berlin' diff --git a/pages/An_introduction_to_gem5.ipynb b/static/An_introduction_to_gem5.ipynb similarity index 100% rename from pages/An_introduction_to_gem5.ipynb rename to static/An_introduction_to_gem5.ipynb diff --git a/static/An_introduction_to_gem5.slides.html b/static/An_introduction_to_gem5.slides.html new file mode 100644 index 0000000000000000000000000000000000000000..5fa57ec1aa4049695bfc83117b7ce1f552a89027 --- /dev/null +++ b/static/An_introduction_to_gem5.slides.html @@ -0,0 +1,12295 @@ + + + + + + + + + + + +An_introduction_to_gem5 slides + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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An introduction to gem5

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Introduction to gem5

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  • Welcome to the redesigned exercises.

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    • Give feedback wether you like this
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  • Goals

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    • Strengthen understanding of the Lectures
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    • Provide some tools for state of the art CA research
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  • Focus on gem5

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    • most widely used Simulator in CA-Research
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    • Lot's of Publications
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  • Exercise sessions are for you

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    • Please participate and ask questions
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gem5 Developers

Developed by a wide Range of Industrial and Academic Institutions

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Developers

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gem5 Basics

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  1. gem5's components can be rearranged, parameterized, extended or replaced easily to suit your needs.
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  3. It simulates the passing of time as a series of discrete events.
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  5. Its intended use is to simulate one or more computer systems in various ways.
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  7. It's more than just a simulator; it's a simulator platform that lets you use as many of its premade components as you want to build up your own simulation system.
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Other SImulators

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SimulatorAccuracySupported processor architecturesLicenseDevelopment Activity
SimicsFunctionally accurateAlpha, ARM, MIPS, PowerPC, SPARC and x86PrivateYes
qemuFunctionally accuratex86, PowerPC, ARM, Sparc, MicroBlaze, Mico32 and othersOpenYes
PTLsimCycle accuratex86OpenYes
SimpleScalarCycle accurateAlpha, ARM, PowerPC and x86OpenNo
OVPsimInstruction accurateOpen RISC, ARM, ARC, MIPS, PowerPC, MicroBlaze and othersPrivateYes
GEM5Cycle accurateAlpha, ARM, x86, SPARC, PowerPC and MIPSOpenYes
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gem5 Features

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  • Configurable CPU models

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    • Simple one-IPC (SimpleAtomic/Timing)
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    • Detailed in-order execution (InOrder)
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    • Detailed out-of-order execution (O3)
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  • Pluggable memory system

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    • Stitch memory system together out of components
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  • Device Models

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    • Enough device models to boot Linux
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  • Many ISAs

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gem5 abstraction levels

gem5 abstraction

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Building gem5

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Building gem5

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  • Recommended virtual machine images with gem5 preinstalled

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  • Should build on 64 Bit Linux, MacOSX, FreeBSD

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  • For details Exercise Sheet 01

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Building gem5

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  • build/<isa>/<binary>

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  • ISAs:

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    • ARM, ALPHA, MIPS, SPARC, POWER, X86
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We use ARM

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    • gem5.debug debug build, symbols, tracing, assert
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    • gem5.opt optimized build, symbols, tracing, assert
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    • gem5.fast optimized build, no debugging, no symbols, no tracing, no assertions
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    • gem5.prof gem5.fast + profiling support
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We use gem5.opt

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gem5 simulation modes

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gem5 simulation modes

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  • Full system (FS)

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    • For booting operating systems
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    • Models bare hardware, including devices
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    • Interrupts, exceptions, privileged instructions, fault handlers
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    • Simulated UART output
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    • Simulated frame buffer output
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    • complex to configure
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    • For running individual applications, or set of applications on MP
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    • Models user-visible ISA plus common system calls
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    • System calls emulated, typically by calling host OS
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    • Simplified address translation model, no scheduling
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    • syscall emulation mode
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Sample Syscall emulation Mode

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Sample Full system ode

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Full systme mode

Syscall Emulation

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gem5 simulation architecture

gem5 architecture

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SimObjects

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  • Everything you care about is an object (C++/Python)

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    • Derived from SimObject base class
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    • Common code for creation, configuration parameters, naming, checkpointing, etc.
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    • CPUs, caches, memory, etc.
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    • Conventional vs. indirect-index cache
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  • Easy replication: cores, multiple systems

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  • MemObjects are special kinds of SimObjects that can be connect using ports

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Ports / MemObjects

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    • e.g. CPU has an instruction and a data port
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  • Ports have distinct roles, and always appear in pairs

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gem5 ports

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Full System Simulation

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Full System Simulation

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Full System SImulation

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