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advanced_computer_architecture
exercises
Commits
23d5f70d
Commit
23d5f70d
authored
Apr 14, 2016
by
Christoph Gerum
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Finish config
parent
23e89224
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5595 deletions
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-5595
aufgaben/blatt01/blatt01.md
aufgaben/blatt01/blatt01.md
+25
-5
aufgaben/blatt01/m5out-automotive-MinorCPU/config.ini
aufgaben/blatt01/m5out-automotive-MinorCPU/config.ini
+0
-761
aufgaben/blatt01/m5out-automotive-MinorCPU/config.json
aufgaben/blatt01/m5out-automotive-MinorCPU/config.json
+0
-1010
aufgaben/blatt01/m5out-automotive-MinorCPU/stats.txt
aufgaben/blatt01/m5out-automotive-MinorCPU/stats.txt
+0
-442
aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.ini
aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.ini
+0
-331
aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.json
...aben/blatt01/m5out-automotive-TimingSimpleCPU/config.json
+0
-411
aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/stats.txt
aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/stats.txt
+0
-481
aufgaben/blatt01/m5out/config.ini
aufgaben/blatt01/m5out/config.ini
+0
-930
aufgaben/blatt01/m5out/config.json
aufgaben/blatt01/m5out/config.json
+0
-1222
aufgaben/blatt01/m5out/stats.txt
aufgaben/blatt01/m5out/stats.txt
+0
-0
aufgaben/blatt01/simple.py
aufgaben/blatt01/simple.py
+19
-2
No files found.
aufgaben/blatt01/blatt01.md
View file @
23d5f70d
...
...
@@ -54,9 +54,9 @@ Für diese Aufgabe ist **keine** Abgabe notwendig.
## Aufgabe 2: Einführung in Instruktionssatzsimulation
Schreiben sie ein Programm das
```Hello World!```
ausgibt in C und kompilieren Sie dieses für ARM.
Schreiben sie ein Programm das
```Hello World!```
ausgibt in C und kompilieren Sie dieses
wie folgt
für ARM.
arm-linux-gnueabihf-gcc -static -O3 hello.c -o hello.elf
Führen Sie dieses im gem5-Simulator aus. Verwenden Sie dafür die bereitgestellte Config-Datei se.py
...
...
@@ -119,11 +119,11 @@ system.mem_ranges = [AddrRange('512MB')]
```
python
system
.
cpu
=
TimingSimpleCPU
()
system
.
cpu
.
createInterruptController
()
```
```
python
system
.
membus
=
CoherentBus
()
system
.
membus
=
SystemXBar
()
```
```
python
...
...
@@ -132,10 +132,30 @@ system.cpu.dcache_port = system.membus.slave
```
```
python
system
.
mem_ctrl
=
DDR
3_16
00_x64
()
system
.
mem_ctrl
=
DDR
4_24
00_x64
()
system
.
mem_ctrl
.
range
=
system
.
mem_ranges
[
0
]
system
.
mem_ctrl
.
port
=
system
.
membus
.
master
```
```
python
process
=
LiveProcess
()
process
.
cmd
=
[
'./hello.elf'
]
system
.
cpu
.
workload
=
process
system
.
cpu
.
createThreads
()
```
```
python
root
=
Root
(
full_system
=
False
,
system
=
system
)
m5
.
instantiate
()
```
```
python
print
"Beginning simulation!"
exit_event
=
m5
.
simulate
()
print
'Exiting @ tick %i because %s'
%
(
m5
.
curTick
(),
exit_event
.
getCause
())
```
Die Konfigurationsdatei finden Sie auch unter
[
aufgaben/blatt01/simple.py
](
/aufgaben/blatt01/simple.py
)
.
...
...
aufgaben/blatt01/m5out-automotive-MinorCPU/config.ini
deleted
100644 → 0
View file @
23e89224
[root]
type
=
Root
children
=
system
eventq_index
=
0
full_system
=
false
sim_quantum
=
0
time_sync_enable
=
false
time_sync_period
=
100000000000
time_sync_spin_threshold
=
100000000
[system]
type
=
System
children
=
clk_domain cpu dvfs_handler mem_ctrl membus
boot_osflags
=
a
cache_line_size
=
64
clk_domain
=
system.clk_domain
eventq_index
=
0
exit_on_work_items
=
false
init_param
=
0
kernel
=
kernel_addr_check
=
true
load_addr_mask
=
1099511627775
load_offset
=
0
mem_mode
=
timing
mem_ranges
=
0:536870911
memories
=
system.mem_ctrl
mmap_using_noreserve
=
false
multi_thread
=
false
num_work_ids
=
16
readfile
=
symbolfile
=
work_begin_ckpt_count
=
0
work_begin_cpu_id_exit
=
-1
work_begin_exit_count
=
0
work_cpus_ckpt_count
=
0
work_end_ckpt_count
=
0
work_end_exit_count
=
0
work_item_id
=
-1
system_port
=
system.membus.slave[2]
[system.clk_domain]
type
=
SrcClockDomain
children
=
voltage_domain
clock
=
1000
domain_id
=
-1
eventq_index
=
0
init_perf_level
=
0
voltage_domain
=
system.clk_domain.voltage_domain
[system.clk_domain.voltage_domain]
type
=
VoltageDomain
eventq_index
=
0
voltage
=
1.000000
[system.cpu]
type
=
MinorCPU
children
=
branchPred dstage2_mmu dtb executeFuncUnits interrupts isa istage2_mmu itb tracer workload
branchPred
=
system.cpu.branchPred
checker
=
Null
clk_domain
=
system.clk_domain
cpu_id
=
-1
decodeCycleInput
=
true
decodeInputBufferSize
=
3
decodeInputWidth
=
2
decodeToExecuteForwardDelay
=
1
do_checkpoint_insts
=
true
do_quiesce
=
true
do_statistics_insts
=
true
dstage2_mmu
=
system.cpu.dstage2_mmu
dtb
=
system.cpu.dtb
enableIdling
=
true
eventq_index
=
0
executeAllowEarlyMemoryIssue
=
true
executeBranchDelay
=
1
executeCommitLimit
=
2
executeCycleInput
=
true
executeFuncUnits
=
system.cpu.executeFuncUnits
executeInputBufferSize
=
7
executeInputWidth
=
2
executeIssueLimit
=
2
executeLSQMaxStoreBufferStoresPerCycle
=
2
executeLSQRequestsQueueSize
=
1
executeLSQStoreBufferSize
=
5
executeLSQTransfersQueueSize
=
2
executeMaxAccessesInMemory
=
2
executeMemoryCommitLimit
=
1
executeMemoryIssueLimit
=
1
executeMemoryWidth
=
0
executeSetTraceTimeOnCommit
=
true
executeSetTraceTimeOnIssue
=
false
fetch1FetchLimit
=
1
fetch1LineSnapWidth
=
0
fetch1LineWidth
=
0
fetch1ToFetch2BackwardDelay
=
1
fetch1ToFetch2ForwardDelay
=
1
fetch2CycleInput
=
true
fetch2InputBufferSize
=
2
fetch2ToDecodeForwardDelay
=
1
function_trace
=
false
function_trace_start
=
0
interrupts
=
system.cpu.interrupts
isa
=
system.cpu.isa
istage2_mmu
=
system.cpu.istage2_mmu
itb
=
system.cpu.itb
max_insts_all_threads
=
0
max_insts_any_thread
=
0
max_loads_all_threads
=
0
max_loads_any_thread
=
0
numThreads
=
1
profile
=
0
progress_interval
=
0
simpoint_start_insts
=
socket_id
=
0
switched_out
=
false
system
=
system
tracer
=
system.cpu.tracer
workload
=
system.cpu.workload
dcache_port
=
system.membus.slave[1]
icache_port
=
system.membus.slave[0]
[system.cpu.branchPred]
type
=
TournamentBP
BTBEntries
=
4096
BTBTagSize
=
16
RASSize
=
16
choiceCtrBits
=
2
choicePredictorSize
=
8192
eventq_index
=
0
globalCtrBits
=
2
globalPredictorSize
=
8192
instShiftAmt
=
2
localCtrBits
=
2
localHistoryTableSize
=
2048
localPredictorSize
=
2048
numThreads
=
1
[system.cpu.dstage2_mmu]
type
=
ArmStage2MMU
children
=
stage2_tlb
eventq_index
=
0
stage2_tlb
=
system.cpu.dstage2_mmu.stage2_tlb
sys
=
system
tlb
=
system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type
=
ArmTLB
children
=
walker
eventq_index
=
0
is_stage2
=
true
size
=
32
walker
=
system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type
=
ArmTableWalker
clk_domain
=
system.clk_domain
eventq_index
=
0
is_stage2
=
true
num_squash_per_cycle
=
2
sys
=
system
[system.cpu.dtb]
type
=
ArmTLB
children
=
walker
eventq_index
=
0
is_stage2
=
false
size
=
64
walker
=
system.cpu.dtb.walker
[system.cpu.dtb.walker]
type
=
ArmTableWalker
clk_domain
=
system.clk_domain
eventq_index
=
0
is_stage2
=
false
num_squash_per_cycle
=
2
sys
=
system
[system.cpu.executeFuncUnits]
type
=
MinorFUPool
children
=
funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index
=
0
funcUnits
=
system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type
=
MinorFU
children
=
opClasses timings
cantForwardFromFUIndices
=
eventq_index
=
0
issueLat
=
1
opClasses
=
system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat
=
3
timings
=
system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type
=
MinorOpClassSet
children
=
opClasses
eventq_index
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type
=
MinorFUTiming
children
=
opClasses
description
=
Int
eventq_index
=
0
extraAssumedLat
=
0
extraCommitLat
=
0
extraCommitLatExpr
=
Null
mask
=
0
match
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats
=
2
suppress
=
false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type
=
MinorOpClassSet
eventq_index
=
0
opClasses
=
[system.cpu.executeFuncUnits.funcUnits1]
type
=
MinorFU
children
=
opClasses timings
cantForwardFromFUIndices
=
eventq_index
=
0
issueLat
=
1
opClasses
=
system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat
=
3
timings
=
system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type
=
MinorOpClassSet
children
=
opClasses
eventq_index
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type
=
MinorFUTiming
children
=
opClasses
description
=
Int
eventq_index
=
0
extraAssumedLat
=
0
extraCommitLat
=
0
extraCommitLatExpr
=
Null
mask
=
0
match
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats
=
2
suppress
=
false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type
=
MinorOpClassSet
eventq_index
=
0
opClasses
=
[system.cpu.executeFuncUnits.funcUnits2]
type
=
MinorFU
children
=
opClasses timings
cantForwardFromFUIndices
=
eventq_index
=
0
issueLat
=
1
opClasses
=
system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat
=
3
timings
=
system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type
=
MinorOpClassSet
children
=
opClasses
eventq_index
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type
=
MinorFUTiming
children
=
opClasses
description
=
Mul
eventq_index
=
0
extraAssumedLat
=
0
extraCommitLat
=
0
extraCommitLatExpr
=
Null
mask
=
0
match
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats
=
0
suppress
=
false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type
=
MinorOpClassSet
eventq_index
=
0
opClasses
=
[system.cpu.executeFuncUnits.funcUnits3]
type
=
MinorFU
children
=
opClasses
cantForwardFromFUIndices
=
eventq_index
=
0
issueLat
=
9
opClasses
=
system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat
=
9
timings
=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type
=
MinorOpClassSet
children
=
opClasses
eventq_index
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type
=
MinorFU
children
=
opClasses timings
cantForwardFromFUIndices
=
eventq_index
=
0
issueLat
=
1
opClasses
=
system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat
=
6
timings
=
system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type
=
MinorOpClassSet
children
=
opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
eventq_index
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type
=
MinorFUTiming
children
=
opClasses
description
=
FloatSimd
eventq_index
=
0
extraAssumedLat
=
0
extraCommitLat
=
0
extraCommitLatExpr
=
Null
mask
=
0
match
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats
=
2
suppress
=
false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type
=
MinorOpClassSet
eventq_index
=
0
opClasses
=
[system.cpu.executeFuncUnits.funcUnits5]
type
=
MinorFU
children
=
opClasses timings
cantForwardFromFUIndices
=
eventq_index
=
0
issueLat
=
1
opClasses
=
system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat
=
1
timings
=
system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type
=
MinorOpClassSet
children
=
opClasses0 opClasses1
eventq_index
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
MemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type
=
MinorFUTiming
children
=
opClasses
description
=
Mem
eventq_index
=
0
extraAssumedLat
=
2
extraCommitLat
=
0
extraCommitLatExpr
=
Null
mask
=
0
match
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats
=
1
suppress
=
false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type
=
MinorOpClassSet
eventq_index
=
0
opClasses
=
[system.cpu.executeFuncUnits.funcUnits6]
type
=
MinorFU
children
=
opClasses
cantForwardFromFUIndices
=
eventq_index
=
0
issueLat
=
1
opClasses
=
system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat
=
1
timings
=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type
=
MinorOpClassSet
children
=
opClasses0 opClasses1
eventq_index
=
0
opClasses
=
system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type
=
MinorOpClass
eventq_index
=
0
opClass
=
IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type
=
MinorOpClass