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---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000036                       # Number of seconds simulated
sim_ticks                                    35545000                       # Number of ticks simulated
final_tick                                   35545000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  12589                       # Simulator instruction rate (inst/s)
host_op_rate                                    14509                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                                7498551                       # Simulator tick rate (ticks/s)
host_mem_usage                                 654352                       # Number of bytes of host memory used
host_seconds                                     4.74                       # Real time elapsed on the host
sim_insts                                       59676                       # Number of instructions simulated
sim_ops                                         68777                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.mem_ctrls.bytes_read::cpu.inst           34304                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::cpu.data           10432                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total              44736                       # Number of bytes read from this memory
system.mem_ctrls.bytes_inst_read::cpu.inst        34304                       # Number of instructions bytes read from this memory
system.mem_ctrls.bytes_inst_read::total         34304                       # Number of instructions bytes read from this memory
system.mem_ctrls.num_reads::cpu.inst              536                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::cpu.data              163                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total                 699                       # Number of read requests responded to by this memory
system.mem_ctrls.bw_read::cpu.inst          965086510                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::cpu.data          293487129                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total            1258573639                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_inst_read::cpu.inst     965086510                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_inst_read::total        965086510                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::cpu.inst         965086510                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::cpu.data         293487129                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total           1258573639                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs                         700                       # Number of read requests accepted
system.mem_ctrls.writeReqs                        228                       # Number of write requests accepted
system.mem_ctrls.readBursts                       700                       # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts                      228                       # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM                  36864                       # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ                    7936                       # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten                    5824                       # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys                   44800                       # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys                14592                       # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ                    124                       # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts                   110                       # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0               157                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1                23                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2                38                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3                33                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4                30                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5                51                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6                25                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7                24                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8                35                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9                47                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10               11                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11                2                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12                6                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13               11                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14               64                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15               19                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0                25                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2                16                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3                 4                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4                 4                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5                 7                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6                 6                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7                 3                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8                16                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9                 5                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13                1                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14                4                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
system.mem_ctrls.totGap                      35540000                       # Total gap between requests
system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::6                   700                       # Read request sizes (log2)
system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::6                  228                       # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0                     323                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1                     165                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2                      63                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3                      22                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4                       3                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15                      2                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16                      3                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17                      5                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20                      7                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22                      7                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24                      7                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples          136                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean    293.176471                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean   193.295149                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev   280.818325                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127           38     27.94%     27.94% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255           39     28.68%     56.62% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383           21     15.44%     72.06% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511           12      8.82%     80.88% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639            5      3.68%     84.56% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767            8      5.88%     90.44% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895            1      0.74%     91.18% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023            4      2.94%     94.12% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151            8      5.88%    100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total          136                       # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples            6                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean             96                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean     53.946094                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev    136.708449                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-31             2     33.33%     33.33% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::32-47             2     33.33%     66.67% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::64-79             1     16.67%     83.33% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::368-383            1     16.67%    100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total             6                       # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples            5                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean             17                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean     16.934320                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev      1.732051                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16                3     60.00%     60.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::17                1     20.00%     80.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::20                1     20.00%    100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total             5                       # Writes before turning the bus around for reads
system.mem_ctrls.totQLat                      6569250                       # Total ticks spent queuing
system.mem_ctrls.totMemAccLat                17369250                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat                    2880000                       # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat                     11404.95                       # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat                30154.95                       # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW                      1037.11                       # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW                       163.85                       # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys                   1260.37                       # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys                    410.52                       # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil                         9.38                       # Data bus utilization in percentage
system.mem_ctrls.busUtilRead                     8.10                       # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite                    1.28                       # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen                       1.51                       # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen                      17.86                       # Average write queue length when enqueuing
system.mem_ctrls.readRowHits                      447                       # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits                      75                       # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate                 77.60                       # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate                63.56                       # Row buffer hit rate for writes
system.mem_ctrls.avgGap                      38297.41                       # Average gap between requests
system.mem_ctrls.pageHitRate                    75.22                       # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy                   635040                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy                   346500                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy                 2722200                       # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy                 278640                       # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy              2034240                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy             21339090                       # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy               124500                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy               27480210                       # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower            875.026588                       # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE      2284750                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF       1040000                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT      30377750                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrls_1.actEnergy                   340200                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy                   185625                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy                 1404000                       # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy                 168480                       # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy              2034240                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy             20988540                       # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy               432000                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy               25553085                       # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower            813.662952                       # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE      3354750                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF       1040000                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT      29757250                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                   15657                       # Number of BP lookups
system.cpu.branchPred.condPredicted             10705                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               920                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                11975                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                    6384                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             53.311065                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                    1762                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
system.cpu_voltage_domain.voltage                   1                       # Voltage in Volts
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   13                       # Number of system calls
system.cpu.numCycles                            71091                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles              22564                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          81968                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                       15657                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches               8146                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                         20882                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    2041                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            14                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           14                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                     10954                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   530                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              44495                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.106484                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.076720                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    27062     60.82%     60.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                     1307      2.94%     63.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                     2383      5.36%     69.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                     1657      3.72%     72.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                     1468      3.30%     76.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                     1469      3.30%     79.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                     1500      3.37%     82.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      725      1.63%     84.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     6924     15.56%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                44495                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.220239                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.153001                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                    19792                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  7799                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                     15380                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   758                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                    766                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved                 2426                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   258                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts                  88524                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  1115                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                    766                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                    20470                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                    2237                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           4040                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                     15428                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                  1554                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  86639                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    62                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                    450                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                    183                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                    735                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands               95743                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                390169                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            97366                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              1613                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                 76144                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                    19599                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                111                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             87                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                      2716                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                15161                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores               12574                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads              2574                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores             2751                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      82842                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 134                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                     78396                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued                78                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined           14199                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined        32047                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             22                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         44495                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.761906                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.106193                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               19992     44.93%     44.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                5431     12.21%     57.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                5003     11.24%     68.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                4636     10.42%     78.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                3346      7.52%     86.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                2823      6.34%     92.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                1865      4.19%     96.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                 830      1.87%     98.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                 569      1.28%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           44495                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                     256     18.89%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                    638     47.08%     65.98% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                   461     34.02%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                 50523     64.45%     64.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                  639      0.82%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd              80      0.10%     65.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc            124      0.16%     65.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult             80      0.10%     65.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                15343     19.57%     85.19% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite               11607     14.81%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                  78396                       # Type of FU issued
system.cpu.iq.rate                           1.102756                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                        1355                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.017284                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads             200754                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             95749                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses        74896                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                1966                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes               1533                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          926                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                  78749                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                    1002                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads             1752                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         2789                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses           24                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation          111                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores         1954                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads          919                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             6                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                    766                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                    1889                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                   106                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               83542                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts               177                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                 15161                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                12574                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 80                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                     12                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                    92                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents            111                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect            225                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          538                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  763                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                 77398                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                 15041                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               998                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                           566                       # number of nop insts executed
system.cpu.iew.exec_refs                        26492                       # number of memory reference insts executed
system.cpu.iew.exec_branches                    12773                       # Number of branches executed
system.cpu.iew.exec_stores                      11451                       # Number of stores executed
system.cpu.iew.exec_rate                     1.088717                       # Inst execution rate
system.cpu.iew.wb_sent                          76032                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                         75822                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                     41163                       # num instructions producing a value
system.cpu.iew.wb_consumers                     78039                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.066549                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.527467                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts           14335                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             112                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               666                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        42228                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.638936                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.490591                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        22109     52.36%     52.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         6486     15.36%     67.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2         4225     10.01%     77.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3         1936      4.58%     82.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4         1502      3.56%     85.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5         1056      2.50%     88.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6          826      1.96%     90.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7          483      1.14%     91.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8         3605      8.54%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        42228                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                60108                       # Number of instructions committed
system.cpu.commit.committedOps                  69209                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                          22992                       # Number of memory references committed
system.cpu.commit.loads                         12372                       # Number of loads committed
system.cpu.commit.membars                          50                       # Number of memory barriers committed
system.cpu.commit.branches                      11781                       # Number of branches committed
system.cpu.commit.fp_insts                        825                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                     58845                       # Number of committed integer instructions.
system.cpu.commit.function_calls                 1320                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu            45316     65.48%     65.48% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult             628      0.91%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     66.38% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd           80      0.12%     66.50% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.50% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.50% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.50% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.50% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc          113      0.16%     66.66% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult           80      0.12%     66.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.78% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead           12372     17.88%     84.66% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite          10620     15.34%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total             69209                       # Class of committed instruction
system.cpu.commit.bw_lim_events                  3605                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                       121998                       # The number of ROB reads
system.cpu.rob.rob_writes                      169369                       # The number of ROB writes
system.cpu.timesIdled                             365                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           26596                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                       59676                       # Number of Instructions Simulated
system.cpu.committedOps                         68777                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.191283                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.191283                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.839431                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.839431                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    84856                       # number of integer regfile reads
system.cpu.int_regfile_writes                   46341                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      1233                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     1193                       # number of floating regfile writes
system.cpu.cc_regfile_reads                    269811                       # number of cc regfile reads
system.cpu.cc_regfile_writes                    35680                       # number of cc regfile writes
system.cpu.misc_regfile_reads                   33390                       # number of misc regfile reads
system.cpu.misc_regfile_writes                    259                       # number of misc regfile writes
system.cpu.dcache.tags.replacements                 2                       # number of replacements
system.cpu.dcache.tags.tagsinuse           118.278353                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs               21574                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               163                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            132.355828                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   118.278353                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.115506                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.115506                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          161                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          150                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.157227                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses             44597                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses            44597                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data        11939                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total           11939                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data         9468                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total           9468                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data           67                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total            67                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           51                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           51                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           49                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           49                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data         21407                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total            21407                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data        21474                       # number of overall hits
system.cpu.dcache.overall_hits::total           21474                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          215                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           215                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          414                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          414                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           11                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           11                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data          629                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            629                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          640                       # number of overall misses
system.cpu.dcache.overall_misses::total           640                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     12811500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     12811500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     22809997                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     22809997                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       187000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       187000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     35621497                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     35621497                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     35621497                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     35621497                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data        12154                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total        12154                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data         9882                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total         9882                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data           78                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total           78                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           54                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           54                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           49                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           49                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data        22036                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total        22036                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data        22114                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total        22114                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017690                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.017690                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.041894                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.041894                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.141026                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.141026                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055556                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055556                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.028544                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.028544                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.028941                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.028941                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59588.372093                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 59588.372093                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55096.611111                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55096.611111                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56631.950715                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56631.950715                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55658.589063                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55658.589063                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          105                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    17.500000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          121                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          121                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          354                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          354                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          475                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          475                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          475                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          475                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           94                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           94                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           60                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           60                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            7                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            7                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            2                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            2                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          154                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          154                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          161                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          161                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6080500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      6080500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3709499                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      3709499                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       434000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       434000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data       133500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total       133500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9789999                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      9789999                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10223999                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     10223999                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007734                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007734                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006072                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006072                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.089744                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.089744                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.037037                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.037037                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006989                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006989                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007280                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.007280                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64686.170213                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64686.170213                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61824.983333                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61824.983333                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        62000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        62000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        66750                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        66750                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63571.422078                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 63571.422078                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63503.099379                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 63503.099379                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements               234                       # number of replacements
system.cpu.icache.tags.tagsinuse           220.548321                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs               10232                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               536                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             19.089552                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   220.548321                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.430758                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.430758                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          302                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.589844                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses             22444                       # Number of tag accesses
system.cpu.icache.tags.data_accesses            22444                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst        10232                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total           10232                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst         10232                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total            10232                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst        10232                       # number of overall hits
system.cpu.icache.overall_hits::total           10232                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          722                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           722                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          722                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            722                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          722                       # number of overall misses
system.cpu.icache.overall_misses::total           722                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     35587499                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     35587499                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     35587499                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     35587499                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     35587499                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     35587499                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst        10954                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total        10954                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst        10954                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total        10954                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst        10954                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total        10954                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.065912                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.065912                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.065912                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.065912                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.065912                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.065912                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49290.164820                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49290.164820                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49290.164820                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49290.164820                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49290.164820                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49290.164820                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          190                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    63.333333                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks          234                       # number of writebacks
system.cpu.icache.writebacks::total               234                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          185                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          185                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          185                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          185                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          185                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          185                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          537                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          537                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          537                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          537                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          537                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          537                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     28065999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     28065999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     28065999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     28065999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     28065999                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     28065999                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.049023                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.049023                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.049023                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.049023                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.049023                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.049023                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52264.430168                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52264.430168                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52264.430168                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52264.430168                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52264.430168                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52264.430168                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp                639                       # Transaction distribution
system.membus.trans_dist::WritebackClean          234                       # Transaction distribution
system.membus.trans_dist::CleanEvict                2                       # Transaction distribution
system.membus.trans_dist::ReadExReq                60                       # Transaction distribution
system.membus.trans_dist::ReadExResp               60                       # Transaction distribution
system.membus.trans_dist::ReadCleanReq            537                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           103                       # Transaction distribution
system.membus.pkt_count_system.cpu.icache.mem_side::system.mem_ctrls.port         1307                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache.mem_side::system.mem_ctrls.port          328                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1635                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache.mem_side::system.mem_ctrls.port        49280                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache.mem_side::system.mem_ctrls.port        10432                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   59712                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples               936                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                     936    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total                 936                       # Request fanout histogram
system.membus.reqLayer0.occupancy             2011500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               5.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2810999                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              7.9                       # Layer utilization (%)
system.membus.respLayer2.occupancy             874750                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              2.5                       # Layer utilization (%)

---------- End Simulation Statistics   ----------