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simple_change-cpu.py 1.58 KB
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import m5
from m5.objects import *

# TODO: Add Caches for working DerivO3CPU!
# system.cpu = TimingSimpleCPU()

# system.cpu = DerivO3CPU()

run_cpu = MinorCPU()
run_cpu.createInterruptController()
switch_cpu = TimingSimpleCPU(switched_out=True)
switch_cpu.createInterruptController()
switch_cpu.clk_domain = SrcClockDomain(clock='1GHz', voltage_domain = VoltageDomain())

switch_cpu_list = [(run_cpu,switch_cpu)]

system = System(cpu = run_cpu)
system.clk_domain = SrcClockDomain(clock='1GHz', voltage_domain = VoltageDomain())
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]
system.membus = SystemXBar()
system.cpu.icache_port = system.membus.slave
system.cpu.dcache_port = system.membus.slave

switch_cpu.icache_port = system.membus.slave
switch_cpu.dcache_port = system.membus.slave

system.system_port = system.membus.slave
system.mem_ctrl = DDR3_1600_x64()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
process = LiveProcess(cmd='/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small')
system.cpu.workload = process
system.cpu.createThreads()

switch_cpu.workload = process
switch_cpu.createThreads()

root = Root(full_system = False, system = system, switch_cpu = switch_cpu)
#root = Root(full_system = False, system = system)
m5.instantiate()


print "Beginning simulation!"
exit_event = m5.simulate(10000)
m5.switchCpus(system,switch_cpu_list)
exit_event = m5.simulate(10000)
m5.switchCpus(system,switch_cpu_list)

print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())