simple.py 1.15 KB
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import m5
from m5.objects import *

system = System()

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system.clk_domain = SrcClockDomain(clock='1GHz', voltage_domain = VoltageDomain())
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system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]

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# system.cpu = TimingSimpleCPU()
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system.cpu = MinorCPU()
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# system.cpu = DerivO3CPU()

# TODO: Add Caches for working DerivO3CPU!
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system.membus = SystemXBar()

system.cpu.icache_port = system.membus.slave
system.cpu.dcache_port = system.membus.slave

system.cpu.createInterruptController()

system.system_port = system.membus.slave

system.mem_ctrl = DDR3_1600_x64()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master

process = LiveProcess()
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# process.cmd = ['/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/hello/hello_world']
process.cmd = ['/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small']
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system.cpu.workload = process
system.cpu.createThreads()

root = Root(full_system = False, system = system)
m5.instantiate()


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print "Beginning simulation!"
exit_event = m5.simulate()
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print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())