Research

Publications

2007
Conference Paper	Pradeep K. Nalla, Joerg Behrend, Prakash M. Peranadam, Jürgen Ruf, Thomas Kropf, and Wolfgang Rosenstiel Grid Based Fast Falsification for Bounded Property Checking Forum on specification and Design Languages (FDL'07), September 18-20, 2007, Barcelona, Spain.
2006
Doctoral Thesis	Prakash Mohan Peranandam Efficient System Traversal and Property Verification by Exploiting Circuit Locality Wilhelm-Schickard-Institut für Informatik, Eberhard-Karls Universität Tübingen, Germany.
Conference Paper	Prakash M. Peranadam, Pradeep K. Nalla, Jürgen Ruf, Roland J. Weiss, Thomas Kropf, and Wolfgang Rosenstiel Fast Falsification Based on Symbolic Bounded Property Checking 43rd Design Automation Conference (DAC'06), July 24-28, 2006, San Francisco, USA.
Poster	Pradeep K. Nalla, Prakash M. Peranandam, J. Ruf, S. Laemmermann, J. Behrend, R.J. Weiss, T. Kropf, and W. Rosenstiel Fast Distributed Property Checking Design Automation and Test in Europe, University Booth (DATE 06), March 6-10, 2006, ICM Messe, Munich, Germany.
2005
Workshop Paper	Prakash M. Peranandam, Pradeep K. Nalla, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, and Wolfgang Rosenstiel Overlap Reduction in Symbolic System Traversal IEEE International High Level Design Validation and Test Workshop 2005 (HLDVT 05), November 30-December 2, 2005, Napa Valley, California, USA. Download: [pdf: 225 KB]
Workshop Paper	Pradeep K. Nalla, Roland J. Weiss, Prakash M. Peranandam, Jürgen Ruf, Thomas Kropf, and Wolfgang Rosenstiel Distributed Symbolic Bounded Property Checking 4th International Workshop on Parallel and Distributed Methods in Verification (PDMC 2005), July 10, 2005, Lisboa, Portugal. Download: [pdf: 265 KB]
2004
Workshop Paper	Prakash M. Peranandam, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, and Wolfgang Rosenstiel Dynamic Guiding of Bounded Property Checking IEEE International High Level Design Validation and Test Workshop 2004 (HLDVT 04), November 10-12, 2004, Sonoma Valley, California, USA. Download: [pdf: 140 KB]
Workshop Paper	Prakash M. Peranandam, Roland J. Weiss, Jürgen Ruf, and Thomas Kropf Transactional Level Verification and Coverage Metrics by Means of Symbolic Simulation 7. GI/ITG/GMM Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, January 2004, Kaiserslautern, Germany. Download: [pdf: 105 KB]
2003
Conference Paper	Jürgen Ruf, Prakash M. Peranadam, Thomas Kropf, and Wolfgang Rosenstiel Using Symbolic Simulation for Bounded Property Checking Forum on specification and Design Languages (FDL'03), September 23-26, 2003, Frankfurt, Germany. Download: [pdf: 150 KB]
Workshop Paper	Jürgen Ruf, Thomas Kropf, and Prakash M. Peranadam Bounded Property Checking with Symbolic Simulation 6. GI/ITG/GMM Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, February 2003, Bremen, Germany. Download: [pdf: 102 KB]
2002
Project Report	Prakash M. Peranandam and Jürgen Ruf Evaluation of Commercial Formal Verification tools FMG Group, Wilhelm-Schickard-Institut für Informatik, Eberhard-Karls Universität Tübingen, Germany.
Project Report	Prakash M. Peranandam and Jürgen Ruf Art of Property Writing FMG Group, Wilhelm-Schickard-Institut für Informatik, Eberhard-Karls Universität Tübingen, Germany.
Master Thesis	Prakash M. Peranandam IP Convergence Layer with Quality of Service Support and its Concept Validation using Pi-Calculus Computational Logic Group, Computer Science Dept., Dresden University of Technology, Dresden, Germany.
2001
Technical Report	Prakash M. Peranandam Computing with Membranes - A Report Download: [ps: 260 KB]