DLX Register Transfer Level
This implementation of the DLX CPU on Register Transfer Level with SystemC is connected to a Memory hierarchy with an answer delay. The whole pipeline is then stalled, if the answer does not come in time. Look at dlx_instr.h to see the whole implemented instruction set. This version does not understand floating point instructions. The description of the debug output is here.
Klick here to view the detailed structure of connection between the modules.
Pipelining is used in processors to allow the parallel execution. Different pipeline stages process parts of the whole execution process. The stages can be executed at the same time. If a instruction depends on previous instructions so that the instructions can't be executed at the same time this is called a data hazard. If a hazard can't be solved by forwarding (passing the calculated values back to previous stages) parts of the pipeline need to be stalled. In a RISC pipeline there are 5 stages. Now a short description, what the stages in this implementation do.
The instruction is read from memory and passed to stage ID.
The instruction is splitted into its opcode, register numbers and immediate values. Then the register values are read and passed to stage EX. If there is branch instruction, the branch is handled by telling stage IF the new programm counter. Stage ID detects hazards with previous instructions and handles the forwarding or data hazard stalling.
The operation is executed and the result is passed to stage MEM. Depending on the input from stage ID we take forwarded values to execute or not.
Memory access instruction (load, store) are processed and then passed to stage WB. Stage MEM handles structure hazard stalling, if the answer from memory takes too long.
The received values are written back to their registers.
Data hazards occur when data is modified. If an operand is modified and read soon after, the first instruction may not have finished writing to the operand and the second instruction may then use incorrect data.
Structure hazards occure, if a stage can't access the device to read the data from. This could be the memory for stage IF oder stage MEM, if the memory has an delay or the register file for stage ID or stage WB, if the register file for example can be accessed by only one stage at a time.
In our implementation structure hazards occur only caused by the memory delay. Stage IF solves them by passing nop (no operation) to stage ID and stage MEM stalles the preceding stages and passes nop to stage WB.
Passing information to previous stages in the pipeline before the instruction reaches the end of the pipeline is called forwarding. In our case this can be forwarding from the ports between stage EX and stage MEM and the ports between stage MEM and stage WB to stage ID or stage EX.
To optimize the access speed to the memory we use two level-1 caches. Our cache is direct mapped and uses the Write-allocate strategy.
Generated on Thu Dec 7 03:20:14 2006 for DLX Processor on Register Transfer Level by
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