On this site the European SystemC Users Group provides systemc-related tools or models for public download. Please keep the particular license agreements for the downloads in mind. If you want to offer your own tools or SystemC models on this page, please contact Axel Braun.
KaSCPar stands for Karlsruhe SystemC Parser Suite. It is a SystemC parser supporting the latest language version with dedicated tokens for SystemC 2.1 keywords. The suite consists of two components for generating either the AST or an elaborated description of the SystemC design, both in XML format for easy usage.
With the VHDL-to-SystemC Converter you can transform VHDL hardware descriptions into SystemC hardware descriptions. (The converter supports only RT-level subsets of VHDL and SystemC, so not every VHDL description could be converted.) The tool runs on SUN Solaris or PC Linux workstations and comes with two little examples.
This is a simulation-based temporal checker tool for SystemC.
With Verilator, you can transform Verilog HDL into SystemC hardware descriptions. The converter supports only synthesizable subsets of Verilog and SystemC. The tool runs on Unix and Windows under Cygwin and includes source.
SystemPerl provides preprocessing of SystemC modules, to reduce the duplicate information necessary to interconnect SystemC modules. It also provides a Perl package to parse and extract information from SystemC designs, and a SystemC mode for Emacs.
© 2007 by European SystemC Users Group